Intel I/O Controller Hub – Part 1

A family of Intel southbridge microchips, I/O Controller Hub (ICH) is used to manage data communications between a CPU and a motherboard. This specifically holds for Intel chipsets based on the Intel Hub Architecture. It is designed to be paired with a second support chip known as a northbridge. The ICH is used to connect and control peripheral devices.

The support chipset eventually emerged as a bottleneck between the processor and the motherboard as CPU speeds increased data transmission between the CPU and support chipset. Starting with the Intel 5 Series, a new architecture was used that incorporated some functions of the traditional north and south bridge chips onto the CPU itself. Also, the remaining functions were consolidated into a single Platform Controller Hub (PCH). This led to the replacement of the traditional two chip setup.

Released in 1999, the first version of the ICH used a proprietary interface (called by Intel Hub Interface) that linked it to the northbridge through an 8-bit wide, 266 MB/s bus contrary to its predecessor, the PIIX, which was connected to the northbridge through an internal PCI bus with a bandwidth of 133 MB/s. The ICH The Hub Interface was a point-to-point connection between different components on the motherboard. In addition to this, the rigid North-South axis substituted the motherboard with a star structure.

Listed below are some more features of the ICH: